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features ? supply voltage up to 40 v ? r dson typically 0.5 at 25c, maximum 1.1 at 150c ? up to 1.5 a output current ? three half-bridge outputs formed by three high-side and three low-side drivers ? capable to switch all kinds of loads such as dc motors, bulbs, r esistors, capacitors and inductors ? no shoot-through current ? very low quiescent current i s < 2 a in standby mode versus total temperature range ? outputs short-circuit protected ? overtemperature protection for each switch and overtemperature prewarning ? undervoltage protection ? various diagnostic functions such as shorted output, open-load, overtemperature and power-supply fail detection ? serial data interface, daisy chain ca pable, up to 2 mhz clock frequency ? so14 power package 1. description the t6818 is a fully protected driver interface designed in 0.8-m bcdmos technol- ogy. they are used to control up to 3 different loads by a microcontroller in automotive and industrial applications. each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 a. the drivers are internally connected to form 3 half-bridges and can be controlled sep- arately from a standard serial data interface. therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. the ic design especially supports the application of h-bridges to drive dc motors. protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. various diagnostic functions and a very low quiescent current in stand-by-mode opens a wide range of applications. automotive qualification (protec- tion against conducted interferences, emc protection and 2-kv esd protection) gives added value and enhanced quality for exacting requirements of automotive applications. triple half- bridge dmos output driver with serial input control t6818 4530h?bcd?09/09
2 4530h?bcd?09/09 t6818 figure 1-1. block diagram di clk inh do c s uv protection s eri a l interf a ce inp u t regi s ter o u tp u t regi s ter h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r o c s n. n. n. n. n. n. p s f o p l s c d n. u . h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p out 3 v s vcc therm a l protection control logic power-on re s et ch a rge p u mp out2 out1 n. n. u . gnd n. u . n. u . n. u . n. u . n. u . u . u . u . u . u . u . u . 3 11 1 7 8 14 212 1 3 5 6 4 10 9 gnd gnd gnd f au lt detect f au lt detect f au lt detect f au lt detect f au lt detect f au lt detect
3 4530h?bcd?09/09 t6818 2. pin configuration figure 2-1. pinning so14 gnd out 3 v s c s di clk gnd gnd out1 out2 vcc inh do gnd 1 2 3 4 5 6 7 14 1 3 12 11 10 9 8 table 2-1. pin description pin symbol function 1 gnd t6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab 2 out3 half-bridge output 3; formed by internally connected power mos high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection ; overtemperature protection; diagnosis for short and open load 3 vs power supply for output stages out1, out2 and out3, internal supply 4 cs chip select input; 5-v cmos logic level input with internal pull up; low = serial communication is enabled, high = disabled 5 di serial data input; 5-v cmos logic level input with intern al pull down; receives serial data from the control device; di expects a 16-bit control word with lsb being transferred first 6 clk serial clock input; 5-v cmos logic level input with in ternal pull down; controls serial data input interface and internal shift register (f max = 2 mhz) 7 gnd ground; see pin 1 8 gnd ground; see pin 1 9 do serial data output; 5-v cmos logic level tri-state out put for output (status) r egister data; sends 16-bit status information to the microcontroller (lsb is transferred first); output will remain tri-stated unless device is selected by cs = low, therefore, several ics can operate on one data output line only. 10 inh inhibit input; 5-v logic input with internal pull down; low = standby, high = normal operation 11 vcc logic supply voltage (5 v) 12 out2 half-bridge output 2; see pin 2 13 out1 half-bridge output 1; see pin 2 14 gnd ground; see pin 1
4 4530h?bcd?09/09 t6818 3. functional description 3.1 serial interface data transfer starts with the falling edge of th e cs signal. data must appear at di synchronized to clk and are accepted on the falling edge of the clk signal. lsb (bit 0, srr) has to be trans- ferred first. execution of new input data is enab led on the rising edge of the cs signal. when cs is high, pin do is in tri-state condition. th is output is enabled on the falling edge of cs. output data will change their state with th e rising edge of clk and stay st able until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer s rr l s 1h s 1l s 2h s 2l s3 h s3 n. u . n. u .n. u .n. u .n. u .n. u . oc s n. u .n. u . c s di clk do tp s 1l s 1h s 2l s 2h s3 l s3 hn. u . n. u .n. u .n. u .n. u .n. u . s cd opl p s f 012 3 4567 8 9 1011121 3 14 15 table 3-1. input data protocol bit input register function 0srr status register reset (high = reset; the bits psf, opl and scd in the output data register are set to low) 1 ls1 controls output ls1 (high = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 ocs overcurrent shutdown (high = overcurrent shutdown is active) 14 n. u. not used 15 n. u. not used
5 4530h?bcd?09/09 t6818 table 3-2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning 1 status ls1 high = output is on, low = output is off; not affected by srr 2 status hs1 high = output is on, low = output is off; not affected by srr 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 scd short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circ uit condition. bits 1 to 6 can be used to detect the shorted switch. 14 opl open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. 15 psf power-supply fail: undervoltage at pin vs detected after power-on reset, the input register has the following status: bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) xxhxxxxxx lllllll the following patterns are used to enable internal test modes of the ic. it is not recommended to use these patterns during normal operation. bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) hhhhhlllllllllll hhhllhhlllllllll hhhllllhhlllllll
6 4530h?bcd?09/09 t6818 3.2 power-supply fail in case of undervoltage at pin vs, the power-supply fail bit (psf) in the output register is set and all outputs are disabled. to detect an undervoltage, its duration has to last longer than the undervoltage detection delay time t duv . the outputs are enabled immediately when supply volt- age recovers normal operation value. the psf bit st ays high until it is reset by the srr bit in the input register. 3.3 open-load detection if the current through a high-side or low-side switch in on-state stays below the open-load detection threshold, the open-load detection bit (opl) in the output register is set. the opl bit stays high until it is reset by the srr bit in the input register. to detect an open load, its duration has to last longer than the open-load detection delay time t dsd . 3.4 overtemperature protection if the junction temperature of one or more output stages exceeds the thermal prewarning thresh- old, t jpw set , the temperature prewarning bit (tp) in the output register is set. when the temperature falls below the t hermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16- bit data word. the status of tp is available at pin do with the falling edge of cs. after the microc ontroller has read this in formation, cs is set high and the data transfer is interrupted without affecting the status of input and output registers. if the junction temperature of one or more outp ut stages exceeds the thermal shutdown thresh- old, t j switch off , all outputs are disabled and the corresponding bits in the output register are set to low. the outputs can be enabled again when the temperature falls below the thermal shutdown threshold, t jswitch on and the srr bit in the input register is set to high. hysteresis of thermal pre- warning and shutdo wn threshold avoids oscillations. 3.5 short-circuit protection the output currents are limited by a current regulator. overcurrent detection is activated by writ- ing a high to the ocs bit in the input register. when the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (t dsd ). the short-circuit detection bit (scd) is set and the corresponding status bit in the output register is set to low. for ocs = low the overcurrent shutdown is inactive. the scd bit is also set if the cur- rent exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. by writing a high to the srr bit in the input register the scd bit is reset and the disabled outputs are enabled. 3.6 inhibit 0 v applied to pin 10 (inh) inhibits the t6818. all output switches are then turned off and switched to tri-state. the data in the output register are deleted. the current consumption is reduced to less than 5 a at pin vs and less than 25 a at pin vcc. the output switches can be activated again by switching pin 10 (inh) to 5 v which initiates an intern al power-on reset.
7 4530h?bcd?09/09 t6818 note: 1. threshold for undervoltage detection 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all values refer to gnd pins. parameters pin symbol value unit supply voltage 3 v vs ?0.3 to +40 v supply voltage t < 0.5 s; i s > ?2 a 3 v vs ?1 v logic supply voltage 11 v vcc ?0.3 to +7 v logic input voltage 4 to 6, 10 v cs ,v di , v clk , v inh ?0.3 to v vcc +0.3 v logic output voltage 9 v do ?0.3 to v vcc +0.3 v input current 4 to 6, 10 i cs ,i di , i clk , i inh ?10 to +10 ma output current 9 i do ?10 to +10 ma output current 2, 12 and 13 i out3 , i out2, i out1 internally limited, se e output specification output voltage 2, 12 and 13 i out3 , i out2, i out1 ?0.3 to +40 v reverse conducting current (t pulse = 150 s) 2, 12 and 13 towards pin 3 i out3 , i out2, i out1 17 a junction temperature range t j ?40 to +150 c storage temperature range t stg ?55 to +150 c 5. thermal resistance parameters test conditions symbol value unit t6818 junction pin measured to gnd pins 1, 7, 8 and 14 r thjp 30 k/w junction ambient r thja 65 k/w 6. operating range parameters symbol value unit supply voltage v vs v uv (1) to 40 v logic supply voltage v vcc 4.75 to 5.25 v logic input voltage v cs ,v di , v clk , v inh ?0.3 to v vcc v serial interface clock frequency f clk 2 mhz junction temperature range t j ?40 to +150 c
8 4530h?bcd?09/09 t6818 note: 1. test pulse 5: v smax = 40 v 7. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) esd s 5.1 2 kv esd (machine model) jedec a115a 200 v 8. electrical characteristics 7.5 v < v vs < 40 v; 4.75 v < v vcc < 5.25 v; inh = high; ?40c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current vs v vs < 20 v, inh = low 3 i vs 1 2 a a 1.2 quiescent current vcc 4.75 v < v vcc < 5.25 v, inh = low 11 i vcc 15 25 a a 1.3 supply current vs v vs < 20 v normal operating, all outputs off 3 i vs 4 6 ma a 1.4 supply current vcc 4.75 v < v vcc < 5.25 v, normal operating 11 i vcc 350 500 a a 1.5 discharge current vs v vs = 32.5 v, inh = low 3 i vs 0.5 5.5 ma a 1.6 discharge current vs v vs = 40 v, inh = low 3 i vs 2.5 10 ma a 2 undervoltage detection, power-on reset 2.1 power-on reset threshold 11 v vcc 3.2 3.9 4.4 v a 2.2 power-on reset delay time after switching on v cc t dpor 30 95 190 s a 2.3 undervoltage-detection threshold v cc = 5 v 3 v uv 5.6 7.0 v a 2.4 undervoltage-detection hysteresis v cc = 5 v 3 v uv 0.6 v a 2.5 undervoltage-detection delay time t duv 10 40 s a 3 thermal prewarning and shutdown 3.1 thermal prewarning set t jpw set 120 145 170 c b 3.2 thermal prewarning reset t jpw reset 105 130 155 c b 3.3 thermal prewarning hysteresis t jpw 15 c b 3.4 thermal shutdown off t j switch off 150 175 200 c b 3.5 thermal shutdown on t j switch on 135 160 185 c b *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs a fter data transmission and switch on output stages to 90% of f inal level. device not in standby for t > 1 ms
9 4530h?bcd?09/09 t6818 3.6 thermal shutdown hysteresis t j switch off 15 cb 3.7 ratio thermal shutdown off/thermal prewarning set t j switch off/ t jpw set 1.05 1.2 b 3.8 ratio thermal shutdown on/thermal prewarning reset t j switch on/ t jpw reset 1.05 1.2 b 4 output specificat ion (out1-out3) 4.1 on resistance i out 1-3 = ?1.3 a 2, 12, 13 r dson1-3 1.1 a 4.2 i out 1-3 = 1.3 a 2, 12, 13 r dson1-3 1.1 a 4.3 high-side output leakage current v out 1-3 = 0 v , output stages off 2, 12, 13 i out1-3 ?15 a a 4.4 low-side output leakage current v out 1-3 = v vs, output stages off 2, 12, 13 i out1-3 200 a a 4.5 high-side switch reverse diode forward voltage i out 1-3 = 1.5 a 2, 12, 13 v out1-3 ? v vs 1.5 v a 4.6 low-side switch reverse diode forward voltage i out 1-3 = ?1.5 a 2, 12, 13 v out 1-3 ?1.5 v a 4.7 high-side overcurrent limitation and shutdown threshold 2, 12, 13 i out1-3 ?2.5 ?2 ?1.5 a a 4.8 low-side overcurrent limitation and shutdown threshold 2, 12, 13 i out1-3 1.5 2 2.5 a a 4.9 overcurrent shutdown delay time t dsd 10 40 s a 4.10 high-side open-load detection threshold 2, 12, 13 i out1-3 ?45 ?30 ?15 ma a 4.11 low-side open-load detection threshold 2, 12, 13 i out1-3 15 30 45 ma a 4.12 open-load detection delay time t dsd 200 600 s a 4.13 high-side output switch on delay (1) v vs = 13 v r load = 30 t don 20 s a 4.14 low-side output switch on delay (1) v vs = 13 v r load = 30 t don 20 s a 4.15 high-side output switch off delay (1) v vs = 13 v r load = 30 t doff 20 s a 8. electrical characteristics (continued) 7.5 v < v vs < 40 v; 4.75 v < v vcc < 5.25 v; inh = high; ?40c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs a fter data transmission and switch on output stages to 90% of f inal level. device not in standby for t > 1 ms
10 4530h?bcd?09/09 t6818 4.16 low-side output switch off delay (1) v vs = 13 v r load = 30 t doff 3sa 4.17 dead time between corresponding high- and low-side switches v vs = 13 v r load = 30 t don ? t doff 1 s a 5 logic inputs di, clk, cs, inh 5.1 input voltage low-level threshold 4-6, 10 v il 0.3 v vcc v a 5.2 input voltage high-level threshold 4-6, 10 v ih 0.7 v vcc v a 5.3 hysteresis of input voltage 4-6, 10 v i 50 700 mv b 5.4 pull-down current pin di, clk, inh v di , v clk, v inh = v cc 5, 6, 10 i pd 10 65 a a 5.5 pull-up current pin cs v cs = 0 v 4 i pu ?65 ?10 a a 6 serial interface ? logic output do 6.1 output-voltage low level i dol = 2 ma 9 v dol 0.4 v a 6.2 output-voltage high level i dol = ?2 ma 9 v doh v vcc ?0.7 v v a 6.3 leakage current (tri-state) v cs = v cc 0v < v do < v vcc 9 i do ?10 10 a a 7 inhibit input ? timing 7.1 delay time from standby to normal operation t dinh 100 s a 8. electrical characteristics (continued) 7.5 v < v vs < 40 v; 4.75 v < v vcc < 5.25 v; inh = high; ?40c < t j < 150 c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of input signal at pin cs a fter data transmission and switch on output stages to 90% of f inal level. device not in standby for t > 1 ms
11 4530h?bcd?09/09 t6818 9. serial interface ? timing no. parameters test condit ions pin timing chart no. (1) symbol min. typ. max. unit type* 8.1 do enable after cs falling edge c do = 100 pf 9 1 t endo 200 ns d 8.2 do disable after cs rising edge c do = 100 pf 9 2 t disdo 200 ns d 8.3 do fall time c do = 100 pf 9 ? t dof 100 ns d 8.4 do rise time c do = 100 pf 9 ? t dor 100 ns d 8.5 do valid time c do = 100 pf 9 10 t doval 200 ns d 8.6 cs setup time 4 4 t cssethl 225 ns d 8.7 cs setup time 4 8 t cssetlh 225 ns d 8.8 cs high time 4 9 t csh 500 ns d 8.9 clk high time 6 5 t clkh 225 ns d 8.10 clk low time 6 6 t clkl 225 ns d 8.11 clk period time 6 ? t clkp 500 ns d 8.12 clk setup time 6 7 t clksethl 225 ns d 8.13 clk setup time 6 3 t clksetlh 225 ns d 8.14 di setup time 5 11 t diset 40 ns d 8.15 di hold time 5 12 t dihold 40 ns d *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. see figure 9-1 on page 12
12 4530h?bcd?09/09 t6818 figure 9-1. serial interface timing with chart numbers c s do 1 2 c s clk 4 5 6 7 9 8 3 di clk do 10 12 11 inp u t s di, clk, c s : high level = 0.7 v cc , low level = 0. 3 v cc o u tp u t do: high level = 0. 8 v cc , low level = 0.2 v cc
13 4530h?bcd?09/09 t6818 10. application circuit 10.1 application notes it is strongly recommended to connect the blocking capacitors at v cc and v s as close as possi- ble to the power supply and gnd pins. recommended value for capacitors at v s : electrolytic capacitor c > 22 f in parallel with a ceramic capacitor c = 100 nf. value for elec- trolytic capacitor depends on external loads, conducted interferences and reverse conducting current i out1,2,3 (see ?absolute maximum ratings? on page 7 ). recommended value for capacitors at v cc : electrolytic capacitor c > 10 f in parallel with a ceramic capacitor c = 100 nf. to reduce ther- mal resistance it is recommended to place coolin g areas on the pcb as close as possible to the gnd pins. negative spikes at the output pins (e .g. negative spikes caused by an inductive load switched off with a high side driver) may activate the overtemperature protection function of the t6818. in this condition, all ou tputs will be switched off simult aneously. if this behavior is not acceptable or compatible with your application functionally, it is necessary, that for switching on required outputs again, the srr bit ( s tatus r egister r eset) is set, to ensure a reset of the over- temperature function. di clk inh do c s uv protection s eri a l interf a ce inp u t regi s ter o u tp u t regi s ter h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r o c s n. n. n. n. n. n. p s f o p l s c d n. u . h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p out 3 v s vcc therm a l protection control logic power-on re s et ch a rge p u mp out2 out1 n. n. u . gnd n. u . n. u . n. u . n. u . n. u . u . u . u . u . u . u . u . 3 11 1 7 8 14 2121 3 5 6 4 10 9 gnd gnd gnd f au lt detect f au lt detect f au lt detect f au lt detect f au lt detect f au lt detect 5 v + + 1 3 v byt41d v s + v b a tt microcontroller u5021m w a tchdog v cc re s et trigger en ab le mm v cc v cc v cc
14 4530h?bcd?09/09 t6818 12. package information 13. revision history 11. ordering information extended type number package remarks t6818-tusy so14 power package, tubed, lead-free t6818-tuqy so14 power package, taped and reeled, lead-free technical drawings according to din specifications package so14 dimensions in mm 0.25 0.10 8.75 0.4 1.27 7.62 1.4 5.2 4.8 3.7 3.8 6.15 5.85 0.2 14 8 17 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4530h-bcd-09/09 ? complete datasheet: ata6828 part removed ? features on page 1 changed ? section 8 ?electrical characteristics number 1.1 on page 8 changed 4530g-bcd-09/05 ? complete datasheet: t6828 changed in ata6828 ? ordering information on page 14 changed ? package drawing on page 15 changed 4530f-bcd-03/05 ? lead-free logo on page 1 added ? table ?ordering information? on page 14 changed 4530e-bcd-07/04 ? table ?ordering information? on page 14 changed 4530d-bcd-04/04 ? features on page 1 changed
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